Typically, a processor's address bus drives each separate signal on the address bus for the duration of a half of a host clock period. These address buses are typically ‘source synchronous’, that is, a clock, or address strobe, is transmitted along with the individual signals on the address bus. Typically, the rising and falling edges of the address strobe are aligned with the center of each address signal.
While driving a signal on the address bus to logical 0, direct current (DC) is consumed by a pull up termination resistor at the receiving side of the signal on the address bus. A pull-up termination resistor is typically on the order of 55 ohms. With a voltage level of about 0.9 volts (V), due to the direct current consumed, the maximum power consumed is about 16 milliWatts (mW) per signal on the address bus. The half a host clock period requirement is primarily driven by the need to meet setup and hold timing on bus lines that are operating over a great distance of about one foot and is operating at the maximum plausible frequency for that bus, given its technology generation.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.